During the design of complex integrated circuits, such as state-of-the-art microprocessors, the question of whether to implement secondary functionality on-chip sometimes turns on whether sufficient "real estate" would remain available on the silicon die after the primary functionality has been implemented. For example, while general purpose registers, a floating point unit and a bus interface would represent primary functionality in a microprocessor, on-chip self-diagnostic circuitry would represent secondary functionality. Thus, the question of whether to include the self-diagnostic circuitry may depend on available space.
One particular problem with the addition of secondary functionality in a digital design, especially self-diagnostic circuitry, is that it frequently involves placing numerous additional registers at widely separated locations around the chip. Not only do the registers themselves take up chip space, but so do the interconnect traces that are required to access them. Moreover, the interconnect traces must be routed in a manner that does not interfere with interconnect traces that are associated with the chip's primary functionality. This problem is felt more severely as the remote registers associated with secondary functionality become larger and more numerous. For example, if thirty-two self-diagnostic registers, each sixty-four bits wide, were placed at various locations within the functional blocks of a microprocessor, more than two thousand interconnect traces could be required to access them for data alone. When control wires are taken into account, the required number of interconnects increases.
Thus, a need exists for an apparatus and method for accessing numerous large remote registers in an integrated circuit chip while using a minimum of interconnect traces.
By way of background, the Institute of Electrical and Electronics Engineers (IEEE) Standard 1149.1, "Test Access Port and Boundary Scan Architecture," also known as the Joint Test Action Group (JTAG) standard, defines a test access port and boundary scan architecture for digital integrated circuits and for the digital portions of mixed analog/digital integrated circuits. The facilities defined by the JTAG standard seek to provide a solution to the problem of testing assembled printed circuit boards and other products based on complex digital integrated circuits and high-density surface-mounting techniques. Therefore, the standard focuses on a "scan chain" of serially-connected registers, each of which is capable of being coupled to a chip pad. Importantly, the scan chains contemplated by the JTAG standard are accessible only by means of an external device connected to the serial port defined by the standard. In some JTAG implementations, numerous different scan chains have been formed on one chip, and the same external serial port has been used to access the different scan chains using an identifier unique to the scan chain of interest. Nevertheless, in all JTAG implementations, an external serial port is needed. Moreover, the JTAG standard does not contemplate or suggest a general-purpose scheme for individually selecting numerous, large and variable-sized registers distributed throughout an integrated circuit device; for reading and writing such registers individually using a minimum of interconnect traces; and for doing so using microprocessor opcodes as opposed to an external device and a serial port.